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STMPE610
S-TouchTM: advanced touchscreen controller with 6-bit port expander
Features

6 GPIOs 1.8 - 3.3 V operating voltage Integrated 4-wire touchscreen controller Interrupt output pin Wakeup feature on each I/O SPI and I2C interface Up to 2 devices sharing the same bus in I2C mode (1 address line) 6-input 12-bit ADC 128-depth buffer touchscreen controller Touchscreen movement detection algorithm 25 kV air-gap ESD protection (system level) 4 kV HBM ESD protection (device level)
QFN16 (3 x 3 mm)
Description
The STMPE610 is a GPIO (general purpose input/output) port expander able to interface a main digital ASIC via the two-line bidirectional bus (I2C). A separate GPIO expander is often used in mobile multimedia platforms to solve the problems of the limited amount of GPIOs typically available on the digital engine. The STMPE610 offers great flexibility, as each I/O can be configured as input, output or specific functions. The device has been designed with very low quiescent current and includes a wakeup feature for each I/O, to optimize the power consumption of the device. A 4-wire touchscreen controller is built into the STMPE610. The touchscreen controller is enhanced with a movement tracking algorithm to avoid excessive data, 128 x 32 bit buffer and a programmable active window feature.
Applications

Portable media players Game consoles Mobile and smartphones GPS
Table 1.
Device summary
Order code STMPE610QTR Package QFN16 Packaging Tape and reel
March 2010
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Contents
STMPE610
Contents
1 2 STMPE610 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
I2C and SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 4.2 4.3 4.4 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 SPI protocol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 5.1.2 5.1.3 Register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Termination of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
SPI timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 7 8 9 10
STMPE610 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 Driver and switch control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11
Touchscreen controller programming sequence . . . . . . . . . . . . . . . . . 39
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Contents
12
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.0.1 Power-up reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14 15 16
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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STMPE610 functional overview
STMPE610
1
STMPE610 functional overview
The STMPE610 consists of the following blocks:

I2C and SPI interface Analog-to-digital converver (ADC) Touchscreen controller (TSC) Driver and switch control unit GPIO controller STMPE610 functional block diagram
Figure 1.
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Pin configuration and functions
2
Pin configuration and functions
Figure 2. STMPE610 pin configuration (top through view)
12 11 10 9
13 14
STMPE610
8 7 6 5
15 16
1
2
3
4
Table 2.
Pin 1 2 3 4 5 6 7 8
Pin assignments
Name YINT A0/Data Out SCLK SDAT VCC Data in NC Y-/GPIO-7 Interrupt output (VCC domain, open drain) I2C address in Reset, Data out in SPI mode (VCC domain) I2C/SPI clock (VCC domain) I2C data/SPI CS (VCC domain) 1.8 Function
-3.3 V supply voltage
SPI Data In (VCC domain)
-
MODE In RESET state, MODE selects the type of serial interface "0" - I2C "1" - SPI Ground IN2/GPIO-2 IN3/GPIO-3 X+/GPIO-4 Supply for touchscreen driver and GPIO Y+/GPIO-5 X-/GPIO-6
9
Mode
10 11 12 13 14 15 16
GND IN2 IN3 X+ Vio Y+ X-
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Pin configuration and functions
STMPE610
2.1
Pin functions
The STMPE610 is designed to provide maximum features and flexibility in a very small pincount package. Most of the pins are multi-functional. The following table shows how to select the pin's function. Table 3. IN2, IN3 pin configuration
GPIO_AF = 1 Pin / control register IN2 IN3 ADC control 1 bit 1 = don't care GPIO-2 GPIO-3 GPIO_AF = 0 ADC control 1 bit 1=0 ADC ADC ADC control 1 bit 1=1 External reference + External reference -
Table 4.
X, Y pin configuration
GPIO_AF = 1 GPIO_AF = 0 TSC control 1 bit 0=0 ADC ADC ADC ADC TSC control 1 bit 0=1 TSC X+ TSC Y+ TSC XTSC Y-
Pin / control register X+ Y+ XY-
TSC control 1 bit 0 = don't care GPIO-4 GPIO-5 GPIO-6 GPIO-7
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I2C and SPI interface
3
3.1
I2C and SPI interface
Interface selection
The STMPE610 interfaces with the host CPU via a I2C or SPI interface. The pin IN_1 allows the selection of interface protocol at reset state. Figure 3. STMPE610 interface
DIN SPI I/F module DOUT CLK CS MUX unit
I2C I/F module
SDAT SCLK A0
Table 5.
Interface selection pins
Pin 3 4 5 7 9 I2C function Address 0 Clock SDATA SPI function Data out Clock CS Data in I2C set to `0' Reset state CPHA for SPI
-
CPOL_N for SPI
-
MODE
-
Set to `1' for SPI
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I2C interface
STMPE610
4
I2C interface
The addressing scheme of STMPE610 is designed to allow up to 2 devices to be connected to the same I2C bus. Figure 4. STMPE610 I2C interface
GND VCC SCLK SDAT SCLK SDAT
STMPE610
ADDR0
AM00753V
Table 6.
I2C address
ADDR0 0 1 Address 0 x 82 0 x 88
For the bus master to communicate to the slave device, the bus master must initiate a Start condition and be followed by the slave device address. Accompanying the slave device adress, is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction. Figure 5.
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT SR tSU:STA P tSU:STO tF tHD:STA
I2C timing diagram
AI00589
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I2C interface
Table 7.
Symbol fSCL tLOW tHIGH tF tHD:STA tSU:STA tSU:DAT tHD:DAT tSU:STO tBUF
I2C timing
Parameter SCL clock frequency Clock low period Clock high period SDA and SCL fall time START condition hold time (after this period the first clock is generated) START condition setup time (only relevant for a repeated start period) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start Min 0 1.3 600 Typ Max 400 Unit kHz s ns ns ns ns ns s ns s
-
600 600 100 0 600 1.3
- - - - - - - - - -
- -
300
- - - - - -
4.1
I2C features
The features that are supported by the I2C interface are listed below:

I2C slave device Operates at 1.8 V Compliant to Philips I2C specification version 2.1 Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and does not respond to any transaction unless one is encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and the bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it does not acknowledge the receipt of the data.
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I2C interface
STMPE610
4.2
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low. Table 8.
Mode
Operating modes
Byte Programming sequence Start, Device address, R/W = 0, Register address to be read Restart, Device address, R/W = 1, Data Read, Stop
Read
1
If no Stop is issued, the Data Read can be continuously performed. If the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after every byte of data being read. Start, Device address, R/W = 0, Register address to be written, Data Write, Stop If no Stop is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then the register address auto-increments internally after every byte of data being written in. For those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operation. Refer to the memory map table for the address ranges that are auto and non-increment.
Write
1
Figure 6.
Read and write modes (random and sequential)
Ack Restart
R/W=0
R/W=1
One byte Read
Device Address
Reg Address
Device Address
Data Read
No Ack
Start
Stop
Ack
Ack
Ack Restart
More than one byte Read
Device Address
Reg Address
Device Address
Data Read
Data Read + 1
No Ack
R/W=0
R/W=1
Data Read + 2
Start
Ack
One byte Write
Device Address
Reg Address
Data to be written
R/W=0
Start
R/W=0
Data to Write + 1
Start
Data to Write + 2
Master Slave
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Ack Stop
Ack
Ack
Ack
Ack
More than one byte Read
Device Address
Reg Address
Data to Write
Ack Stop
Ack
Ack
Ack
Ack
Stop
Ack
STMPE610
I2C interface
4.3
Read operation
A write is first performed to load the register address into the Address Counter but without sending a Stop condition. Then, the bus master sends a reStart condition and repeats the Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the content of the addressed byte. If no additional data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a Stop condition. If the bus master acknowledges the data byte, then it can continue to perform the data reading. To terminate the stream of data bytes, the bus master must not acknowledge the last output byte, and be followed by a Stop condition. If the address of the register written into the Address Counter falls within the range of addresses that has the auto-increment function, the data being read will be coming from consecutive addresses, which the internal Address Counter automatically increments after each byte output. After the last memory address, the Address Counter 'rolls-over' and the device continues to output data from the memory address of 0x00. Similarly, for the register address that falls within a non-increment range of addresses, the output data byte comes from the same address (which is the address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a low state, then the slave device terminates and switches back to its idle mode, waiting for the next command.
4.4
Write operations
A write is first performed to load the register address into the Address Counter without sending a Stop condition. After the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the Address Counter). The slave device again acknowledges and the bus master terminates the transfer with a Stop condition. If the bus master needs to write more data, it can continue the write operation without issuing the Stop condition. Whether the Address Counter autoincrements or not after each data byte write depends on the address of the register written into the Address Counter. After the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a Stop condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the next data byte write.
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SPI interface
STMPE610
5
SPI interface
The SPI interface in STMPE610 uses a 4-wire communication connection (DATA IN, DATA OUT, CLK, CS). In the diagram, "Data in" is referred to as MOSI (master out slave in) and "DATA out" is referred to as MISO (master in slave out).
5.1
SPI protocol definition
The SPI (serial peripheral interface) follows a byte sized transfer protocol. All transfers begin with an assertion of CS_n signal (falling edge). The protocol for reading and writing is different and the selection between a read and a write cycle is dependent on the first captured bit on the slave device. A '1' denotes a read operation and a '0' denotes a write operation. The SPI protocol defined in this section is shown in Figure 3. The following are the main features supported by this SPI implementation.

Support of 1 MHz maximum clock frequency. Support for autoincrement of address for both read and write. Full duplex support for read operation. Daisy chain configuration support for write operation. Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins. Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.
5.1.1
Register read
The following steps need to be followed for register read through SPI. 1. 2. 3. 4. Assert CS_n by driving a '0' on this pin. Drive a '1' on the first SCL launch clock on MOSI to select a read operation. The next 7 bits on MOSI denote the 7-bit register address (MSB first). The next address byte can now be transmitted on the MOSI. If the autoincrement bit is set, the following address transmitted on the MOSI is ignored. Internally, the address is incremented. If the autoincrement bit is not set, then the following byte denotes the address of the register to be read next. Read data is transmitted by the slave device on the MISO (MSB first), starting from the launch clock following the last address bit on the MOSI. Full duplex read operation is achieved by transmitting the next address on MOSI while the data from the previous address is available on MISO. To end the read operation, a dummy address of all 0's is sent on MOSI.
5. 6. 7.
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SPI interface
5.1.2
Register write
The following steps need to be followed for register write through SPI. 1. 2. 3. 4. 5. Assert CS_n by driving a '0' on this pin. Drive a '0' on the first SCL launch clock on MOSI to select a write operation. The next 7 bits on MOSI denote the 7-bit register address (MSB first). The next byte on the MOSI denotes data to be written. The following transmissions on MOSI are considered byte-sized data. The register address to which the following data is written depends on whether the autoincrement bit in the SPICON register is set. If this bit has been set previously, the register address is incremented for data writes.
5.1.3
Termination of data transfer
A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If the last launch clock is detected, it is assumed that the data transfer is successful.
5.2
SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the "SDAT" and "A0" pins during power-up reset. The following four modes are defined according to this setting. Table 9. SPI timing modes
CPOL 0 0 1 1 CPHA (ADDR pin) 0 1 0 1 Mode 0 1 2 3
CPOL_N (SDAT pin) 1 1 0 0
The clocking diagrams of these modes are shown in ON reset. The device always operates in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on the next transaction defined by the CS_n pin being deasserted and asserted.
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SPI interface
STMPE610
5.2.1
SPI timing definition
Table 10.
Symbol
SPI timing specification
Timing Description Min Typ Max CS_n falling to first capture clock Clock low period Clock high period Launch clock to MOSI data valid Launch clock to MISO data valid Data on MOSI valid Last clock edge to CS_n high CS_n high period CS_n high to first clock edge CS_n high to tri-state on MISO Unit
tCSS
1
- - - - - - - - - -
- - -
20
s
tCL tCH
500 500
ns ns
tLDI
- -
1
ns
tLDO
330
s
tDI
- - - - -
s
tCCS
1
s
tCSH tCSCL
2 300
s ns
tCSZ
1
s
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STMPE610 Figure 7. SPI timing specification
SPI interface
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STMPE610 registers
STMPE610
6
STMPE610 registers
This section lists and describes the registers of the STMPE610 device, starting with a register map and then provides detailed descriptions of register types. Table 11.
Address 0x00 0x02 0x03 0x04 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x20 0x21 0x22 0x30 0x32
Register summary map table
Register name CHIP_ID ID_VER SYS_CTRL1 SYS_CTRL2 SPI_CFG INT_CTRL INT_EN INT_STA GPIO_EN GPIO_INT_STA ADC_INT_EN ADC_INT_STA GPIO_SET_PIN GPIO_CLR_PIN GPIO_MP_STA GPIO_DIR GPIO_ED GPIO_RE GPIO_FE GPIO_AF ADC_CTRL1 ADC_CTRL2 ADC_CAPT ADC_DATA_CH0 ADC_DATA_CH1 Bit 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 Type R R R/W R/W R/W R/W R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Reset value 0x0811 0x03 0x00 0x0F 0x01 0x00 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x9C 0x01 0xFF 0x0000 0x0000 Function Device identification Revision number 0x01 for engineering sample 0x03 for final silicon Reset control Clock control SPI interface configuration Interrupt control register Interrupt enable register interrupt status register GPIO interrupt enable register GPIO interrupt status register ADC interrupt enable register ADC interrupt status register GPIO set pin register GPIO clear pin register GPIO monitor pin state register GPIO direction register GPIO edge detect register GPIO rising edge register GPIO falling edge register Alternate function register ADC control ADC control To initiate ADC data acquisition ADC channel 0 ADC channel 1
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STMPE610 Table 11.
Address 0x38 0x3A 0x3C 0x3E 0x40 0x41 0x42 0x44 0x46 0x48 0x4A 0x4B 0x4C 0x4D 0x4F 0x51 0x52
STMPE610 registers Register summary map table (continued)
Register name ADC_DATA_CH4 ADC_DATA_CH5 ADC_DATA_CH6 ADC_DATA_CH7 TSC_CTRL TSC_CFG WDW_TR_X WDW_TR_Y WDW_BL_X WDW_BL_Y FIFO_TH FIFO_STA FIFO_SIZE TSC_DATA_X TSC_DATA_Y TSC_DATA_Z TSC_DATA_XYZ TSC_FRACT_X YZ TSC_DATA TSC_I_DRIVE TSC_SHIELD Bit 16 16 16 16 8 8 16 16 16 16 8 8 8 16 16 8 32 Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R R Reset value 0x0000 0x0000 0x0000 0x0000 0x90 0x00 0x0FFF 0x0FFF 0x0000 0x0000 0x00 0x20 0x00 0x0000 0x0000 0x0000 0x00000000 Function ADC channel 4 ADC channel 5 ADC channel 6 ADC channel 7 4-wire touchscreen controller setup Touchscreen controller configuration Window setup for top right X Window setup for top right Y Window setup for bottom left X Window setup for bottom left Y FIFO level to generate interrupt Current status of FIFO Current filled level of FIFO Data port for touchscreen controller data access Data port for touchscreen controller data access Data port for touchscreen controller data access Data port for touchscreen controller data access Select the range and accuracy of the pressure measurement Data port for touchscreen controller data access Touchscreen controller drive I Touchscreen controller shield
0x56
8
RW
0x00
0x57 0x58 0x59
8 8 8
R R/W R/W
0x00 0x00 0x00
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System and identification registers
STMPE610
7
System and identification registers
Table 12.
Address 0x00 0x02 0x03 0x04 0x08
System and identification registers map
Register name CHIP_ID ID_VER SYS_CTRL1 SYS_CTRL2 SPI_CFG Bit 16 8 8 8 8 Type R R R/W R/W R/W Reset 0x0811 0x03 0x00 0x0F 0x01 Function Device identification Revision number 0x01 for engineering sample 0x03 for final silicon Reset control Clock control SPI interface configuration
CHIP_ID
Address: Type: Reset: Description: 0x00 R 0x0811 16-bit device identification
Device identification
ID_VER
Address: Type: Reset: Description: 0x02 R 0x03 16-bit revision number
Revision number
SYS_CTRL1
7 6 5 4 RESERVED 3 2 1 SOFT_RESET
Reset control
0 HIBERNATE
Address: Type: Reset: Description:
0x03 R/W 0x00 The reset control register enables to reset the device
[7:2] RESERVED [1] SOFT_RESET: Reset the STMPE610 using the serial communication interface [0] HIBERNATE: Force the device into hibernation mode. Forcing the device into hibernation mode by writing `1' to this bit would disable the hot-key feature. If the hot-key feature is required, use the default auto-hibernation mode.
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System and identification registers
SYS_CTRL2
7 6 5 4 3 RESERVED 2 GPIO_OFF 1 TSC_OFF
Clock control
0 ADC_OFF
Address: Type: Reset: Description:
0x04 R/W 0x0F This register enables to switch off the clock supply
[7:3] RESERVED [2] GPIO_OFF: Switch off the clock supply to the GPIO 1: Switches off the clock supply to the GPIO [1] TSC_OFF: Switch off the clock supplyto the touchscreen controller 1: Switches off the clock supply to the touchscreen controller [0] ADC_OFF: Switch off the clock supply to the ADC 1: Switches off the clock supply to the ADC
SPI_CFG
7 6 5 RESERVED 4 3 2 AUTO_INCR
SPI interface configuration
1 SPI_CLK_MOD1 0 SPI_CLK_MOD0
Address: Type: Reset: Description:
0x08 R/W 0x01 SPI interface configuration register
[7:3] RESERVED [2] AUTO_INCR: This bit defines whether the SPI transaction follows an addressing scheme that internally autoincrements or not [1] SPI_CLK_MOD1: This bit reflects the value of the SCAD/A0 pin during power-up reset [0] SPI_CLK_MOD0: This bit reflects the value of the SCAD/A0 pin during power-up reset
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Interrupt system
STMPE610
8
Interrupt system
The STMPE610 uses a 2-tier interrupt structure. The ADC interrupts and GPIO interrupts are ganged as a single bit in the "interrupt status register". The interrupts from the touchscreen controller can be seen directly in the interrupt status register. Figure 8. Interrupt system diagram
FIFO status TSC touch
Interrupt status AND
GPIO interrupt status AND GPIO interrupt enable
Interrupt enable
ADC interrupt status AND ADC interrupt enable
AM00752V2
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Interrupt system
INT_CTRL
7 6 5 RESERVED 4 3 2 INT_POLARITY
Interrupt control register
1 INT_TYPE 0 GLOBAL_INT
Address: Type: Reset: Description:
0x09 R/W 0x00 The interrupt control register is used to enable the interruption from a system-related interrupt source to the host.
[7:3] RESERVED [2] INT_POLARITY: This bit sets the INT pin polarity 1: Active high/rising edge 0: Active low/falling edge [1] INT_TYPE: This bit sets the type of interrupt signal required by the host 1: Edge interrupt 0: Level interrupt [0] GLOBAL_INT: This is master enable for the interrupt system 1: Global interrupt 0: Stops all interrupts
INT_EN
7 GPIO 6 ADC 5 RESERVED 4 FIFO_EMPTY 3 FIFO_FULL 2 FIFO_0FLOW
Interrupt enable register
1 FIFO_TH 0 TOUCH_DET
Address: Type: Reset: Description:
0x0A R/W 0x00 The interrupt enable register is used to enable the interruption from a system related interrupt source to the host.
[7] GPIO: Any enabled GPIO interrupts [6] ADC: Any enabled ADC interrupts [5] RESERVED [4] FIFO_EMPTY: FIFO is empty [3] FIFO_FULL: FIFO is full [2] FIFO_OFLOW: FIFO is overflowed [1] FIFO_TH: FIFO is equal or above threshold value [0] TOUCH_DET: Touch is detected
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Interrupt system
STMPE610
INT_STA
7 GPIO 6 ADC 5 RESERVED 4 FIFO_EMPTY 3 FIFO_FULL 2 FIFO_OFLOW
Interrupt status register
1 FIFO_TH 0 TOUCH_DET
Address: Type: Reset: Description:
0x0B R 0x10 The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless of whether the INT_EN bits are enabled, the INT_STA bits are still updated. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
[7] GPIO: Any enabled GPIO interrupts [6] ADC: Any enabled ADC interrupts [5] RESERVED [4] FIFO_EMPTY: FIFO is empty [3] FIFO_FULL: FIFO is full [2] FIFO_OFLOW: FIFO is overflowed [1] FIFO_TH: FIFO is equal or above threshold value. This bit is set when FIFO level equals to threshold value. It will only be asserted again if FIFO level drops to < threshold value, and increased back to threshold value. [0] TOUCH_DET: Touch is detected
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STMPE610
Interrupt system
GPIO_INT_EN
7 6 5 4 3 IEG[x]
GPIO interrupt enable register
2 1 0
Address: Type: Reset: Description:
0x0C R/W 0x10 The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless of whether the IER bits are enabled, the ISR bits are still updated. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
[7:0] IEG[x]: Interrupt enable GPIO mask (where x = 7 to 0) 1: Writing `1' to the IE[x] bit enables the interruption to the host
GPIO_INT_STA
7 6 5 4 3
GPIO interrupt status register
2 1 0
ISG[x]
Address: Type: Reset: Description:
0x0D R/W 0x00 The GPIO interrupt status register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless of whether or not the GPIO_STA bits are enabled, the GPIO_STA bits are still updated. The ISG[7:0] bits are the interrupt status bits corresponding to the GPIO[7:0] pins. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
[7:0] ISG[x]: GPIO interrupt status (where x = 7 to 0) Read: Interrupt status of the GPIO[x]. Reading the register will clear any bits that have been set to '1' Write: Writing to this register has no effect
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Analog-to-digital converter
STMPE610
9
Analog-to-digital converter
An 8-input,12-bit analog-to-digital converter (ADC) is integrated in the STMPE610. The ADC can be used as a generic analog-to-digital converter, or as a touchscreen controller capable of controlling a 4-wire resistive touchscreen. Table 13.
Address 0x20 0x21 0x22 0x30 0x32 0x38 0x3A 0x3C 0x3E
AddINT_EN
ADC controller register summary table
Register name ADC_CTRL1 ADC_CTRL2 ADCCapture ADC_DATA_CH0 ADC_DATA_CH1 ADC_DATA_CH4 ADC_DATA_CH5 ADC_DATA_CH6 ADC_DATA_CH7 Size 8 8 8 8 8 8 8 8 8 ADC control ADC control To initiate ADC data acquisition ADC channel 0 (IN3/GPIO-3) ADC channel 1 (IN2/GPIO-2) ADC channel 4 (TSC) ADC channel 5 (TSC) ADC channel 6 (TSC) ADC channel 7 (TSC) Description
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Analog-to-digital converter
ADC_CTRL1
7 RESERVED 6 5 4 3 MOD_12B 2 RESERVED 1 SAMPLE_TIME2 SAMPLE_TIME1 SAMPLE_TIME0
ADC control 1
0 RESERVED REF_SEL
Address: Type: Reset: Description:
0x20 R/W 0x9C ADC control register
[7] RESERVED [6:4] SAMPLE_TIMEn: ADC conversion time in number of clock 000: 36 001: 44 010: 56 011: 64 100: 80 101: 96 110: 124 111: Not valid [3] MOD_12B: Selects 10 or 12-bit ADC operation 1: 12 bit ADC 0: 10 bit ADC [2] RESERVED [1] REF_SEL: Selects between internal or external reference for the ADC 1: External reference 0: Internal reference [0] RESERVED
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Analog-to-digital converter
STMPE610
ADC_CTRL2
7 6 5 4 RESERVED 3 2 1 ADC_FREQ_1
ADC control 2
0 ADC_FREQ_0
Address: Type: Reset: Description:
0x21 R/W 0x01 ADC control.
[7] RESERVED [6] RESERVED [5] RESERVED [4] RESERVED [3] RESERVED [2] RESERVED [1:0] ADC_FREQ: Selects the clock speed of ADC 00: 1.625 MHz typ. 01: 3.25 MHz typ. 10: 6.5 MHz typ. 11: 6.5 MHz typ.
ADC_CAPT
7 6 5 4 3 CH[7:0] 2
ADC channel data capture
1 0
Address: Type: Reset: Description:
0x22 R/W 0xFF
To initiate ADC data acquisition [7:0] CH[7:0]: ADC channel data capture Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect. Reads '1' if conversion is completed. Reads '0' if conversion is in progress.
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Analog-to-digital converter
ADC_DATA_CHn
11 10 9 8 7 6 5 DATA[11:0] 4
ADC channel data registers
3 2 1 0
Address: Type: Reset: Description:
Add address R/W 0x0000
ADC data register 0-7 (DATA_CHn=0 -7) [11:0] DATA[11:0]: ADC channel data If TSC is enabled, CH3-0 is used for TSC and all readings to these channels give 0x0000
The ADC in STMPE610 operates on an internal RC clock with a typical frequency of 6.5 MHz. The total conversion time in ADC mode depends on the "SampleTime" setting, and the clock division field 'Freq'. The following table shows the conversion time based on 6.5 MHz, 3.25 MHz and 1.625 MHz clock. Table 14. ADC conversion time
Conversion time in ADC clock 36 44 56 64 80 96 124 6.5 MHz (154 ns) 5.5 s (180 kHz) 6.8 s (147 kHz) 8.6 s (116 kHz) 9.9 s (101 kHz) 3.25 MHz (308 ns) 11 s (90 kHz) 13.6 s (74 kHz) 17.2 s (58 kHz) 19.8 s (51 kHz) 1.625 MHz (615 ns) 22 s (45 kHz) 27 s (36 kHz) 34.4 s (29 kHz) 39.6 s (25 kHz) 49.2 s (20 kHz) 59.2 s (17 kHz) 56.4 s (13 kHz)
Sample time setting 000 001 010 011 100 101 110
12.3 s (81.5 kHz) 24.6 s (41 kHz) 14.8 s (67.6 kHz) 28.8 s (33 kHz) 19.1 s (52.3 kHz) 38.2 s (26 kHz)
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Touchscreen controller
STMPE610
10
Touchscreen controller
The STMPE610 is integrated with a hard-wired touchscreen controller for 4-wire resistive type touchscreen. The touchscreen controller is able to operate completely autonomously, and will interrupt the connected CPU only when a pre-defined event occurs. Figure 9. Touchscreen controller block diagram
Movement & window tracking FIFO FIFO & interrupt control
10/12 bit ADC
Switch & drivers
s
Driver & switch control
10.1
Driver and switch control unit
The driver and switch control unit allows coordination of the ADC and the MUX/switch. With the coordination of this unit, a stream of data is produced at a selected frequency. The touchscreen drivers can be configured with 2 current ratings: 20 mA or 50 mA. In the case where multiple touch-down on the screen is causing a short, the current from the driver is limited to these values. Tolerance of these current setting is +/- 25%.
Movement tracking
The "Tracking Index" in the TSC_CTRL register specifies a value, which determines the distance between the current touch position and the previous touch position. If the distance is shorter than the tracking index, it is discarded. The tracking is calculated by summation of the horizontal and vertical movement. Movement is only reported if: (Current X - Previously Reported X) + (Current Y - Previously Reported Y) > Tracking Index If pressure reporting is enabled (X/Y/Z), an increase in pressure will override the movement tracking and report the new data set, even if X/Y is within the previous tracking index. This is to ensure that a slow touch will not be discarded. If pressure data is not used, select X/Y mode in touchscreen data acquisition. (Opmode field in TSCControl register).
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Touchscreen controller
Window tracking
The -WDW_X and WDW_Y registers allow to pre-set a sub-window in the touchscreen such that any touch position that is outside the sub-window will be discarded. Figure 10. Window tracking
Top right coordinates
Active window
Bottom left coordinates
FIFO
FIFO has a depth of 128 sectors. This is enough for 128 sets of touch data at maximum resolution (2 x 12 bits). FIFO can be programmed to generate an interrupt when it is filled to a pre-determined level.
Sampling
The STMPE610 touchscreen controller has an internal 180 kHz, 12-bit ADC able to execute autonomous driving/sampling. Each "sample" consists of 4 ADC readings that provide the X and Y locations, as well as the touch pressure. Figure 11. Sampling
ADC takes X reading Drive X Settling period Drive Y
ADC takes Y reading Settling period
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Touchscreen controller
STMPE610
Oversampling and averaging function
The STMPE610 touchscreen controller can be configured to oversample by 2/4/8 times and provide the averaged value as final output. This feature helps to reduce the effect of surrounding noise. Table 15.
Address 0x40 0x41 0x42 0x44 0x46 0x48 0x4A 0x4B 0x4C 0x4D 0x4F 0x51 0x52 0x56 0x57 0x58 0x59
Touchscreen controller register summary table
Register name TSC_CTRL TSC_CFG WDW_TR_X WDW_TR_Y WDW_TR_X WDW_TR_Y FIFO_TH FIFO_CTRL_STA FIFO_SIZE TSC_DATA_X TSC_DATA_Y TSC_DATA_Z TSC_DATA_XYZ TSC_FRACT_Z TSC_DATA TSC_I_DRIVE TSC_SHIELD Bit 8 8 16 16 16 16 8 8 8 16 16 8 32 8 8 8 8 Type R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R R/W R/W Function 4-wire touchscreen controller setup TSC configuration register Window setup for top right X Window setup for top right Y Window setup for bottom left X Window setup for bottom left Y FIFO level to generate interrupt Current status of FIFO Current filled level of FIFO Data port for TSC data access Data port for TSC data access Data port for TSC data access Data port for TSC data access TSC_FRACT_Z TSC data access port TSC_I_DRIVE TSC_SHIELD
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STMPE610
Touchscreen controller
TSC_CTRL
7 TSC_STA 6 5 TRACK 4 3
Touchscreen controller control register
2 OP_MOD 1 0 EN
Address: Type: Reset: Description:
0x40 R/W 0x90 4-wire touchscreen controller (TSC) setup.
[7] TSC_STA: TSC status Reads '1' when touch is detected Reads '0' when touch is not detected Writing to this register has no effect [6:4] TRACK: Tracking index 000: No window tracking 001: 4 010: 8 011: 16 100: 32 101: 64 110: 92 111: 127 [3:1] OP_MOD: TSC operating mode 000: X, Y, Z acquisition 001: X, Y only 010: X only 011: Y only 100: Z only This field cannot be written on, when EN = 1 [0] EN: Enable TSC
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Touchscreen controller
STMPE610
TSC_CFG
7 6 5 4 AVE_CTRL_1 AVE_CTRL_0
Touchscreen controller configuration register
3 2 SETTLING_2 1 SETTLING_1 0 SETTLING_0 TOUCH_DET TOUCH_DET TOUCH_DET _DELAY_2 _DELAY_1 _DELAY_0
Address: Type: Buffer: Reset: Description:
0x41 R/W
Touchscreen controller configuration register.
[7:6] AVE_CTRL_1/0: Average control 00=1 sample 01=2 samples 10=4 samples 11=8 samples [5:3] TOUCH_DET_DELAY_2/1/0: Touch detect delay 000 - 10 s 001 - 50 s 010 = 100 s 011 = 500 s 100 = 1 ms 101 = 5 ms 110 = 10 ms 111 = 50 ms [2:0] SETTLING: Panel driver settling time(1) 000 = 10 s 001 = 100 s 010 = 500 s 011 =1 ms 100 = 5 ms 101 = 10 ms 110 = 50 ms 111 =100 ms
1. For large panels (> 6"), a capacitor of 10 nF is recommended at the touchscreen terminals for noise filtering. In this case, settling time of 1 ms or more is recommended.
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STMPE610
Touchscreen controller
WDW_TR_X
7 6 5 TR_X [11:0] 4
Window setup for top right X
3 2 1 0
Address: Type: Reset: Description:
0x42 R/W 0x0FFF
Window setup for top right X coordinates [11:0] TR_X: bit 11:0 of top right X coordinates
WDW_TR_Y
7 6 5 TR_Y [11:0] 4
Window setup for top right Y
3 2 1 0
Address: Type: Reset: Description:
0x44 R/W 0x0FFF
Window setup for top right Y coordinates [11:0] TR_X: bit 11:0 of top right Y coordinates
WDW_BL_X
7 6 5 BL_X [11:0] 4
Window setup for bottom left X
3 2 1 0
Address: Type: Reset: Description:
0x46 R/W 0x0000
Window setup for bottom left X coordinates [11:0] BL_X: bit 11:0 of bottom left X coordinates
WDW_BL_Y
7 6 5 BL_Y [11:0] 4
Window setup for bottom left Y
3 2 1 0
Address: Type: Reset: Description:
0x48 R/W 0x0000
Window setup for bottom left Y coordinates [11:0] BL_X: bit 11:0 of bottom left Y coordinates
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Touchscreen controller
STMPE610
FIFO_TH
7 6 5 4 3 FIFO_TH 2 1
FIFO threshold
0
Address: Type: Reset: Description:
0x4A R/W 0x00
Triggers an interrupt upon reaching or exceeding the threshold value. This field must not be set as zero. [7:0] FIFO_TH: Touchscreen controller FIFO threshold
FIFO_CTRL_STA
7 FIFO_OFLOW 6 FIFO_FULL 5 FIFO_EMPTY 4 FIFO_TH_TRIG 3 2 RESERVED 1
FIFO threshold
0 FIFO_RESET
Address: Type: Reset: Description:
0x4B R/W 0x20
Current status of FIFO.. [7] FIFO_OFLOW: Reads 1 if FIFO is overflow [6] FIFO_FULL: Reads 1 if FIFO is full [5] FIFO_EMPTY: Reads 1 if FIFO is empty [4] FIFO_TH_TRIG: 0 = Current FIFO size is still below the threshold value 1 = Current FIFO size is at or beyond the threshold value [3:1] RESERVED [0] FIFO_RESET: Write '0' : FIFO put out of reset mode Write '1' : Resets FIFO. All data in FIFO will be cleared. When TSC is enabled, FIFO resets automatically.
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Touchscreen controller
FIFO_SIZE
7 RESERVED 6 5 4 3 FIFO_SIZE 2 1
FIFO size
0
Address: Type: Reset: Description:
0x4C R 0x00 Current number of samples available
[7:0] FIFO_SIZE: Number of samples available
TSC_DATA_X
11 10 9 8 7 6 5 DATAY[11:0] 4 3 2
TSC_DATA_X
1 0
Address: Type: Reset: Description:
0x4D R 0x0000 Bit 11:0 of Y dataTSC_DATA_Y
[11:0] DATAY[11:0]: Bit 11:0 of Y data
TSC_DATA_Y
11 10 9 8 7 6 5 DATAY[11:0] 4 3 2 1 0
Address: Type: Reset: Description:
0x4F R 0x0000 Bit 11:0 of Y data
[11:0] DATAY[11:0]: bit 11:0 of Y data
TSC_DATA_Z
7 6 5 4 3 DATAZ[7:0] 2 1
TSC_DATA_Z
0
Address: Type: Reset: Description:
0x51 R 0x0000 Bit 7:0 of Z data
[7:0] DATAZ[7:0]: bit 7:0 of Z data
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Touchscreen controller
STMPE610
TSC_DATA
7 6 5 4 3 DATA 2
Touchscreen controller DATA
1 0
Address: Type: Reset: Description:
0x57 (auto-increment), 0xD7 (non-auto-increment) R 0x00 Data port for TSC data access
[11:0] DATA: data bytes from TSC FIFO
The data format from the TSC_DATA register depends on the setting of "OpMode" field in TSC_CTRL register. The samples acquired are accessed in "packed samples". The size of each "packed sample" depends on which mode the touchscreen controller is operating in. The TSC_DATA register can be accessed in 2 modes:

Autoincrement Non autoincrement
To access the 128-sets buffer, the non autoincrement mode should be used. Table 16. Touchscreen controller DATA register
Number of bytes to read from TSC_DATA 4 3 2 2 1
TSC_CTRL in operation mode
Byte0
Byte1
Byte2
Byte3
000 001 010 011 100
[11:4] of X [11:4] of X [11:4] of X [11:4] of Y [7:0] of Z
[3:0] of X [11:8] of Y [3:0] of X [11:8] of Y [3:0] of X [3:0] of Y -
[7:0] of Y [7:0] of Y -
[7:0] of Z -
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Touchscreen controller
TSC_FRACTION_Z
7 6 5 RESERVED 4 3
Touchscreen controller FRACTION_Z
2 1 FRACTION_Z 0
Address: Type: Reset: Description:
0x56 R 0x00 This register allows to select the range and accuracy of the pressure measurement
[7:3] RESERVED [2:0] FRACTION_Z: 000: Fractional part is 0, whole part is 8 001: Fractional part is 1, whole part is 7 010: Fractional part is 2, whole part is 6 011: Fractional part is 3, whole part is 5 100: Fractional part is 4, whole part is 4 101: Fractional part is 5, whole part is 3 110: Fractional part is 6, whole part is 2 111: Fractional part is 7, whole part is 1
TSC_I_DRIVE
7 6 5 4 RESERVED 3 2
Touchscreen controller drive I
1 0 DRIVE
Address: Type: Reset: Description:
0x58 R/W 0x00 This register sets the current limit value of the touchscreen drivers
[7:1] RESERVED [0] DRIVE: maximum current on the touchscreen controller (TSC) driving channel 0: 20 mA typical, 35 mA max 1: 50 mA typical, 80 mA max
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Touchscreen controller
STMPE610
TSC_SHIELD
7 6 RESERVED 5 4 3 X+ 2 X-
Touchscreen controller shield
1 Y+ 0 Y-
Address: Type: Reset: Description:
0x59 R 0x00 Writing each bit would ground the corresponding touchscreen wire
[7:4] RESERVED [3:0] SHIELD[3:0]: Write 1 to GND X+, X-, Y+, Y- lines
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Touchscreen controller programming sequence
11
Touchscreen controller programming sequence
The following are the steps to configure the touchscreen controller (TSC): a) b) c) Disable the clock gating for the touchscreen controller and ADC in the SYS_CFG2 register. Configure the touchscreen operating mode and the window tracking index. A touch detection status may also be enabled through enabling the corresponding interrupt flag. With this interrupt, the user is informed through an interrupt when the touch is detected as well as lifted. Configure the TSC_CFG register to specify the "panel voltage settling time", touch detection delays and the averaging method used. A windowing feature may also be enabled through TSCWdwTRX, TSCWdwTRY, TSCWdwBLX and TSCWdwBLY registers. By default, the windowing covers the entire touch panel. Configure the TSC_FIFO_TH register to specify the threshold value to cause an interrupt. The corresponding interrupt bit in the interrupt module must also be enabled. This interrupt bit should be masked off during data fetching from the FIFO in order to prevent an unnecessary trigger of this interrupt. Upon completion of the data fetching, this bit can be re-enabled By default, the FIFO_RESET bit in the TSC_FIFO_CTRL_STA register holds the FIFO in Reset mode. Upon enabling the touchscreen controller (through the EN bit in TSC_CTRL), this FIFO reset is automatically deasserted. The FIFO status may be observed from the TSC_FIFO_CTRL_STA register or alternatively through the interrupt. Once the data is filled beyond the FIFO threshold value, an interrupt is triggered (assuming the corresponding interrupt is being enabled). The user is required to continuously read out the data set until the current FIFO size is below the threshold, then, the user may clear the interrupt flag. As long as the current FIFO size exceeds the threshold value, an interrupt from the touchscreen controller is sent to the interrupt module. Therefore, even if the interrupt flag is cleared, the interrupt flag will automatically be asserted, as long as the FIFO size exceeds the threshold value. The current FIFO size can be obtained from the TSC_FIFO_Sz register. This information may assists the user in how many data sets are to be read out from the FIFO, if the user intends to read all in one shot. The user may also read a data set by a data set. The TSC_DATA_X register holds the X-coordinates. This register can be used in all touchscreen operating modes. The TSC_DATA_Y register holds the Y-coordinates. TSC_DATA_Y register holds the Y-coordinates. The TSC_DATA_Z register holds the Z value. TSC_DATA_Z register holds the Zcoordinates.
d) e)
f)
g)
h)
i)
j) k) l)
m) The TSCDATA_XYZ register holds the X, Y and Z values. These values are packed into 4 bytes. This register can only be used when the touchscreen operating mode is 000 and 001. This register is to facilitate less byte read. n) For the TSC_FRACT_Z register, the user may configure it based on the touchscreen panel resistance. This allows the user to specify the resolution of the
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Touchscreen controller programming sequence
STMPE610
Z value. With the Z value obtained from the register, the user simply needs to multiply the Z value with the touchscreen panel resistance to obtain the touch resistance. o) The TSC_DATA register allows facilitation of another reading format with minimum I2C transaction overhead by using the non autoincrement mode (or equivalent mode in SPI). The data format is the same as TSC_DATA_XYZ, with the exception that all the data fetched are from the same address. Enable the EN bit of the TSC_CTRL register to start the touch detection and data acquisition. During the auto-hibernate mode, a touch detection can cause a wake-up to the device only when the TSC is enabled and the touch detect status interrupt mask is enabled. In order to prevent confusion, it is recommended that the user not mix the data fetching format (TSC_DATA_X, TSC_DATA_Y, TSC_DATA_Z, TSC_DATA_XYZ and TSC_DATA) between one reading and the next. It is also recommended that the user should perform a FIFO reset and TSC disabling when the ADC or TSC setting are reconfigured.
p) q)
r)
s)
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GPIO controller
12
GPIO controller
A total of 6 GPIOs are available in the STMPE610 port expander device. Most of the GPIOs share physical pins with some alternate functions. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to minimize power consumption. A group of registers are used to control the exact function of each of the 6 GPIOs. The registers and their respective addresses are listed in the following table. Table 17.
Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
GPIO control registers
Register name GPIO_SET_PIN GPIO_CLR_PIN GPIO_MP_STA GPIO_DIR GPIO_ED GPIO_RE GPIO_FE GPIO_ALT_FUNCT Size (bit) 8 8 8 8 8 8 8 8 Function Set pin register Clear pin state Monitor pin state Set pin direction Edge detect status Rising edge detection enable Falling edge detection enable Alternate function register
All GPIO registers are named as GPIO-x, where x represents the functional group.
7 GPIO-7
6 GPIO-6
5 GPIO-5
4 GPIO-4
3 GPIO-3
2 GPIO-2
1 RESERVED
0 RESERVED
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GPIO controller
STMPE610
GPIO_SET_PIN
Address: Type: Reset: Description: 0x10 R/W 0x00 GPIO set pin register.
GPIO set pin register
Writing 1 to this bit causes the corresponding GPIO to go to 1 state. Writing 0 has no effect.
GPIO_CLR_PIN
Address: Type: Reset: Description: 0x11 R/W 0x00 GPIO clear pin state register.
Clear pin state register
Writing `1' to this bit causes the corresponding GPIO to go to 0 state. Writing `0' has no effect.
GPIO_MP_STA
Address: Type: Reset: Description: 0x12 R/W 0x00 GPIO monitor pin state.
GPIO monitor pin state register
Reading this bit yields the current state of the bit. Writing has no effect.
GPIO_DIR
Address: Type: Reset: Description: 0x13 R/W 0x00 GPIO set pin direction register.
GPIO set pin direction
Writing `0' sets the corresponding GPIO to input state, and `1' sets it to output state. All bits are `0' on reset.
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GPIO controller
GPIO_ED_STA
Address: Type: Reset: Description: 0x14 R/W 0x00
GPIO edge detect status
GPIO edge detect status register. An edge transition has been detected.
GPIO_RE
Address: Type: Reset: Description: 0x15 R/W 0x00 GPIO rising edge detection enable register.
Rising edge register
Setting this bit to `1' would enable the detection of the rising edge transition. The detection would be reflected in the GPIO edge detect status register.
GPIO_FE
Address: Type: Reset: Description: 0x16 R/W 0x00
Falling edge detection enable register
Setting this bit to `1' would enable the detection of the falling edge transition. The detection would be reflected in the GPIO edge detect status register.
GPIO_ALT_FUNCT
Address: Type: Reset: Description: 0x17 R/W 0x0F
Alternate function register
Alternate function register. "`0' sets the corresponding pin to function as touchscreen/ADC, and `1' sets it into GPIO mode.
On power-up reset, all GPIOs are set as input.
Power supply
The STMPE610 GPIO operates from a separate supply pin (VIO). This dedicated supply pin provides a level-shifting feature to the STMPE610. The GPIO remains valid until VIO is removed. The host system may choose to turn off Vcc supply while keeping VIO supplied. However it is not allowed to turn off supply to VIO, while keeping the Vcc supplied. The touchscreen is always powered by VIO. For better resolution and noise immunity, VIO above 2.8 V is advised.
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GPIO controller
STMPE610
12.0.1
Power-up reset (POR)
The STMPE610 is equipped with an internal POR circuit that holds the device in reset state, until the VIO supply input is valid. The internal POR is tied to the VIO supply pin.
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STMPE610
Maximum rating
13
Maximum rating
Stressing the device above the ratings listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 18.
Symbol VCC VIO ESD T TSTG TJ Supply voltage GPIO supply voltage ESD protection on each GPIO pin (air discharge) Operating temperature Storage temperature Thermal resistance junction-ambient
Absolute maximum ratings
Parameter Value 4.5 4.5 4 -40 - 85 -65 - 155 96 Unit V V kV C/W C/W C/W
13.1
Recommended operating conditions
Table 19.
Symbol Vcc VIO
Power consumption
Value Parameter Core supply voltage Vio >= Vcc I/O supply voltage Touchscreen controller at 100 Hz sampling VCC= 1.8 - 3.3 V Touchscreen controller at 100 Hz sampling VIO = 1.8 V Touchscreen controller at 100 Hz sampling VIO = 3.3 V Hibernate state, no I2C/SPI activity VCC = 1.8 V 1.65 Test condition Min 1.65 Typ Max 3.6 3.6 V V Unit
- -
0.5
ICC-active
Core supply current
-
1.0
uA
IIO-active
I/O supply current
-
0.8
1.2
mA
IIO-active
I/O supply current
- -
2.0
2.8
mA
ICChibernate
Core supply current
0.5
1
uA
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Maximum rating Table 19.
Symbol
STMPE610 Power consumption (continued)
Value Parameter Test condition Min Hibernate state, no I2C/SPI activity VIO = 1.8 - 3.3 V Hibernate state, no I2C/SPI activity VIO = 3.3 V Typ Max Unit
- -
0.5
1
A
IIOhibernate
I/O supply current
1.0
3.0
A
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Electrical specifications
14
Electrical specifications
Table 20. DC electrical characteristics (-40 C to 85 C, all GPIOs comply to JEDEC
standard JESD-8-7) Value Symbol VIL VIH VOL VOH Parameter Input voltage low state Input voltage high state Test condition Min VIO = 1.8 - 3.3 V VIO = 1.8 - 3.3 V -0.3 V 0.80 VIO -0.3 V 0.85 VIO -0.3 V 0.85 VCC Typ Max 0.20 VIO VIO + 0.3 V 0.15 VIO V V V V Unit
Output voltage low state VIO = 1.8 V, IOL = 4 mA Output voltage high VIO = 3.3 V, state IOL = 8 mA
- - - - - -
-
0.15 VCC VCC +0.3V
VOL Output voltage low state VCC = 1.8 V, (I2C/SPI) IOL = 4 mA VCC = 3.3 V, VOH Output voltage high 2C/SPI) state IOL = 8 mA (I
V V
Table 21.
Symbol
AC electrical characteristics (-40 C to 85 C)
Value Parameter Test condition Min Typ Max VCC = 1.8 - 3.3 V VCC = 1.8 V VCC = 3.3 V 400 800 1000 Unit
CLKI2Cmax I2C maximum SCLK CLKSPImax SPI maximum clock
- - -
- - -
kHz kHz kHz
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Electrical specifications Table 22. ADC specification (-40 C to 85 C)
Value Parameter Full-scale input span Absolute input range Input capacitance Leakage current Resolution No missing codes Integral linearity error Offset error Gain error Noise Power supply rejection ratio Throughput rate Including internal Vref Test condition Min 0 Typ Max Vref
STMPE610
Unit
- - - -
11
- -
25 0.1 12
V V pF A bits bits bits LSB LSB Vrms dB ksps
VCC +0.2
- - - -
6 7 18
- - - - - -
4 5 14 70 50 180
- - -
Table 23.
Switch drivers specification
Value Test condition Min Typ 5.5 7.3 Max Unit
Parameter ON resistance X+, Y+ ON resistance X-, YDrive current
Duration 100 ms
- - -
- -
50
mA
-
Table 24.
Voltage reference specification
Value Test condition Min Typ 2.50 25 300 1 Max 2.55 V Ppm/C G 2.45 Unit
Parameter Internal reference voltage Internal reference drift
Internal reference ON Output impedance Internal reference OFF
- - -
- - -
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Package mechanical data
15
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 12. Package outline for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch
7185330_F
1. Drawing not to scale.
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Package mechanical data Table 25.
STMPE610
Package mechanical data for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch
Millimeters
Symbol Min A A1 A3 b D D2 E E2 e K L r 0.80 Typ 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 Max 1.00 0.05
- -
0.18
-
0.30
-
1.55
-
1.80
-
1.55
-
1.80
- -
0.30 0.09
- -
0.50
-
-
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Package mechanical data Figure 13. Recommended footprint for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch
Table 26.
Footprint dimensions
Millimeters
Symbol Min A B C D E F G Typ 3.8 3.8 0.5 0.3 0.8 1.5 0.35 Max
- - - - - - -
- - - - - - -
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Package mechanical data Figure 14. Carrier tape for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch
STMPE610
7875978
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Package mechanical data Figure 15. Reel information for QFN16 (3 x 3 x 1 mm) - 0.50 mm pitch
7875978_14
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Package mechanical data Figure 16. Marking specifications
STMPE610
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Revision history
16
Revision history
Table 27.
Date 07-Apr-2009 23-Sep-2009 12-Mar-2010
Document revision history
Revision 1 2 3 Initial release. Removed "Temperature sensor" from Section 1, Figure 1 and Figure 8. Updated: In the SYS_CTRL2 register, the 3rd bit is reserved. Updated: Title of the document and ESD value in Table 18. Changes
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STMPE610
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